Improving Software Design Comprehension

VeriSIM

Topic: Software Engineering

Target audience: Third year CS/IT undergraduates

No of students trained: 100

Research Team: Prajish Prasad, Sridhar Iyer

When students graduate and enter the software industry, they spend your first several months working on existing projects and developing additional features based on new requirements. These activities require them to explicitly understand software design diagrams.

Software design is usually represented as multiple diagrams(UML is the most common representation) which describe different aspects of the system (like its structure and behavior) at different levels of abstraction.

Prajish, through his experiments with students found that students have difficulties in understanding the relationship between these diagrams, and are unable to simulate scenarios based on the design.

In order to solve this problem, he has developed VeriSIM – a learning environment which trains students in a strategy called “design tracing” which enables students to trace the sequence of data and function changes across different diagrams for a particular behavior.

Publications

Prajish Prasad (2018, August). Developing Students’ Cognitive Processes Required for Software Design Verification. In Proceedings of the 2018 ACM Conference on International Computing Education Research (pp.284-285). ACM.